Method and circuit for de-skewing data in a communication system

ABSTRACT

Method and circuitry for de-skewing data in data communication networks such as a SONET. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. The information bits sent to the framer chip are searched in order to detect the training sequence. The training sequences contain clear transition patterns at which all 16 bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit must be a skewed bit. Based on the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected back. After the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition. The multiplexing logic circuitry includes at least three registers coupled to the inputs of the multiplexing logic circuitry.

BACKGROUND OF THE INVENTION

[0001] The present invention relates generally to the field of communication systems and more specifically to a method and circuit for de-skewing data in communication systems.

[0002] A data-bus typically comprises a number of parallel interface lines for communicating data signals in parallel. However, the data signals in all of the parallel lines are not always received by a receiver at the same time, even though the data signals are simultaneously transmitted in synchronization with the transmitter system clock. This results in a condition known as data skew. Data skew refers to the delay and/or early arrival of a data bit relative to other data bits in the parallel lines. Conventional systems for de-skewing data on computer data-buses are generally well known. While systems for de-skewing data have been applied to other contexts, such systems are inapplicable to certain communication networks such as SONET (synchronous optical network). In part, this is due to certain unique attributes possessed by SONETs. Another reason relates to certain interface standards that SONETs must meet.

[0003] SONET is a transport mechanism for multiplexing high-speed data from multiple networks onto fiber optic cabling. It interconnects IP (Internet protocol) networks, ATM (asynchronous transfer mode) switches, T1s and the like via fiber optic networks known as SONET rings. For example, an IP network in San Francisco may be interconnected to a New York IP network via a SONET ring. Since different network types are interconnected, routers are employed for converting protocols from one network type to another. In the case of IP protocols, routers are used for converting the IP packets into a form suitable for transmission on the SONET ring.

[0004] A board or line card in the router receives the IP packets on one end, performs the necessary conversions and sends out the packets at the other end. Among other components, a line card includes a framer chip for framing/de-framing IP packets, and a system chip for performing protocol conversion and for controlling packet traffic. The framer chip communicates with the system side through an interface known as the SPI-4 (system packet interface). The SPI-4 interface is a standard defined by a consortium of communication companies for packet and cell transfer between a physical layer device (i.e., the framer chip) and a link layer device (i.e., the system chip). As defined, the SPI-4 interface has a 16 bit data bus at a clock speed of 622 MHz. Other features of the SPI-4 interface include a transmit control signal (TCTL) and a receive control signal (RCTL) between the system chip and the framer chip. Further, the SPI-4 interface requires the system chip to periodically send training sequences to the framer chip for detecting data skew. Alternatively, the training sequences are periodically sent from the framer chip to the system chip.

[0005] As noted, data skew refers to the delay and/or early arrival of a data bit relative to other data bits in the parallel lines. The skew may be due to a combination of board layout, environment temperature variation and other reasons. To facilitate understanding the present invention, FIG. 1 is a block diagram of a board level connection 100 for the transmit direction between a system chip 100 and a framer chip 101 illustrating data skew on the 16 bit data-bus.

[0006] In FIG. 1, the transmit direction has 16 data transmit lines and a transmit control line between system chip 100 and framer chip 101. Each transmit line has a delay buffer 104-1 thorough 104-17, respectively, each representing the total delay caused by board level wires as well as the output delay from system chip 100 and the input delay from framer chip 101. Because the data lines may not be of exactly the same length or same width for all 16 data transmit lines, data bit on each line may each arrive at their destinations 103-1 through 103-17 at different times. Given a clock frequency of 622 MHz (i.e., clock period=1.6 ns) the time differences among the 16 data-bits can be as long as 1 clock cycle or greater thus causing data skew among the data lines. When data skew occurs, all of the data-bits are no longer aligned.

[0007] Therefore, there is a need to resolve the aforementioned disadvantage of data communication networks such as SONET and the present invention meets this need.

BRIEF SUMMARY OF THE INVENTION

[0008] According to a first aspect of the present invention, a method of de-skewing data in a data communication network such as the synchronous optical network (SONET) is disclosed. The data is sent from a system chip to a framer chip where the data is de-skewed. To detect data skew, the system chip sends a training sequence to the framer chip. In accordance with the present invention, information bits sent to the framer chip are searched in order to detect the training sequence.

[0009] The training sequences contain clear transition patterns at which all of the multiple parallel bits of the transmit data and the TCTL signal line are inverted. If any bit does not invert, this bit is detected as a skewed bit. Based on the value of the data one clock cycle before and one clock cycle after this transition, the skewed bit can be corrected. In one embodiment after the data skew is detected, a multiplexing logic circuitry is used to correct the skew based on one clock cycle either before or after the transition.

[0010] According to another aspect of the present invention, a method of de-skewing data in a SONET is taught. The SONET has a system chip for communicating a plurality of data-bits to a framer chip through a data-bus. Among other acts, the method includes: forwarding a sequence of training bits from the system chip to the framer chip; and thereafter, receiving the sequence of training bits at the framer chip. Next, the sequence of training bits received is compared to the sequence forwarded in order to determine if one training bit has a maximum skew of +/−1 clock cycle. If the training bit is not skewed, a no-skew input is selected for receiving the plurality of data-bits.

[0011] On the other hand, if the training bit is skewed, it is determined whether there is a late skew or an early skew. If a late skew exists, the late skew is corrected by selecting a late skew input for receiving the plurality of data-bits. It should be noted that the data-bits at the second input are at least one clock cycle earlier than the data-bits for the no skew input. If there is an early skew, however, the early skew is corrected by selecting an early skew input for receiving the plurality of data-bits. The data-bits at the early skew are at least one clock cycle later than the data-bits at the no skew input.

[0012] According to another aspect of the present invention, after determining that a data skew exists, any one of three inputs is selected to receive the plurality of data-bits, wherein a first input is selected if there is no data skew, a second input is selected if there is a late skew, or a third input is selected if an early skew occurs.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a block diagram of a board level connection between a system chip and a framer chip illustrating data skew on an exemplary 16 bit data-bus.

[0014]FIG. 1A is an exemplary block diagram of a board level connection between a system chip and a framer chip illustrating both the receive and transmit directions.

[0015]FIG. 2 is a table illustrating an exemplary training sequence for de-skewing bit arrival times on data and control line in accordance with a first embodiment of the present invention.

[0016]FIG. 3 is a received training sequence illustrating early data skew, the training sequence being received by the framer chip.

[0017]FIG. 4 is a training sequence for illustrating late data skew, the training sequence being received by a framer chip.

[0018]FIG. 5 is a training sequence for illustrating both early and late data skew, the training sequence being received by a framer chip.

[0019]FIG. 6 is a block diagram of a multiplexor circuitry for correcting data skew on a 16 bit data-bus in accordance with an exemplary embodiment of the present invention.

[0020]FIG. 7 shows a state diagram (machine) for detecting a training sequence in accordance with an exemplary embodiment of the present invention.

[0021]FIG. 8 is a block diagram of an exemplary control circuit for the selection lines of the multiplexor of FIG. 6.

[0022]FIG. 9 is a block diagram of an alternate multiplexor circuitry for correcting data skew.

[0023]FIG. 10 is a generic circuit for correcting bit arrival time in accordance with the present invention.

[0024] A further understanding of the nature and advantages of the present invention herein may be gained by reference to the remaining portions of the specification and the attached drawings. Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with respect to the accompanying drawings. In the drawings, the same reference numbers indicate identical or functionally similar elements.

DETAILED DESCRIPTION OF THE INVENTION

[0025] In a communication system such as a synchronous optical network (SONET), a framer chip communicates with a system chip through a system packet interface (SPI) standard such as SPI-4 (10 Gb/s) or SPI-5 (40 Gb/s). The SPI-4, for example, has a 16 bit data-bus in the transmit direction (TDAT[15:0]) where [15:0] indicates bits 0 through 15, and has an associated transmit control signal (TCTL). Further, the bit data bus has a 16 bit data-bus in the receive direction (RDAT[15:0]) with a corresponding receive control signal (RCTL). According to a first aspect of the present invention, a method of de-skewing TDAT[15:0] in the SONET is disclosed.

[0026] Prior to de-skewing, it is determined if a data skew exists by sending a training sequence from the system chip to the framer chip. If there is no skew, a no-skew input of a multiplexor circuit is selected for receiving the plurality of data-bits. If a skew does exist, it is determined whether there is a late skew or an early skew. If there is a late skew, it is corrected by selecting a late skew input for receiving the plurality of data-bits. Otherwise, the early skew is corrected by selecting an early skew input of the multiplexor.

[0027]FIG. 2 is a table illustrating an exemplary training sequence 200 for de-skewing bit arrival times on data lines 105-2 through 105-17 (FIG. 1) and control line 106 in accordance with a first embodiment of the present invention. In the present embodiment, training sequence 200 is compliant with the OIF-SPI4-01.0 and 02.0, phases 1 and 2 defining an interface between physical and link layer, or peer to peer entities operating at an OC-192 rate, and an interface for physical and link layer devices, respectively.

[0028] To de-skew data arriving at an interface, training sequence 200 is sent either by system chip 100 (FIG. 1) or framer chip 100 depending on which interface de-skewing is required. For example, if data de-skew is required on framer chip 101 interface, training sequence 200 is sent by system chip 100 to the framer chip interface. When framer chip 101 receives the training sequence, it compares the received sequence with the training sequence forwarded by system chip 101. If the sequences match up, there is no data skew. Otherwise, data skew is present. Data de-skew will also be needed by system chip 100 in the receive direction. When this is required, training sequence 200 is sent by framer chip 101 in the receive direction as shown in FIG. 1A. In FIG. 1A, both the receive and transmit directions are shown. The training sequence for the receive direction is sent as RDAT[0] through RDAT[15], that is via lines 107-17 through 107-2.

[0029] As shown, training sequence 200 comprises one or more repetitions of a known training pattern of 1s and 0s. The training pattern includes training data words TDAT [i] (transmit data) where i is the number of data lines. Training sequence 200 also includes a number of TCTL (transmit control) words and a cycle wherein each word is sent. In this exemplary embodiment, the length of training is at least 21 cycles as shown at 202 wherein the number of cycles depend on α, a system dependent variable. As noted, if the data received at the destination is the same as those in FIG. 2, there is no skew among the data lines. When there are skews among the 16 bit data lines, there can be three situations illustrated in FIGS. 3, 4 and 5.

[0030]FIG. 3 is a received training sequence 300 illustrating early data skew, the training sequence being received by framer chip 101. In FIG. 3, during cycle 11, bit 10 of transmit data (TDAT[10]) is one clock cycle ahead of the other bits. That is, TDAT[10] is 0 where it should be 1. Because TDAT[10] should be 0 during cycle 12 and not cycle 11, it is one cycle early.

[0031]FIG. 4 is a received training sequence 400 illustrating late data skew, the training sequence being received by framer chip 101. In FIG. 4, in cycle 12, TDAT[11] is 1 clock cycle behind the other bits in the table.

[0032]FIG. 5 is a received training sequence 500 illustrating both early and late data skew, the training sequence being received by framer chip 101. In FIG. 5, TDAT[10] is 1 clock cycle ahead, while TDAT[8] is 1 clock cycle behind the other bits.

[0033] The above figures illustrate the basic idea of de-skew. First, a known data sequence is sent through the interface. Next, the data at the destination is compared bit by bit with the original data. For each bit, if the value at the destination matches the value at the source, there is no skew for this bit. If the value at the destination mismatches the value at the source, a data skew has taken place. It should be observed that, in this example, the data at each bit remains the same value for 10 clock cycles and then it is inverted, and remains at the inverted value for another 10 clock cycles, when it is inverted back. Thus every 20 clock cycles makes up a complete training period. It is to be understood that the specific numbers of clock cycles are exemplary.

[0034] The total number of periods in the training process is determined by the value α. The tasks for the de-skew include the following: (1) searching for the training sequences; (2) identifying the transition instances; (3) comparing the received values at the destinations with the source values, if there is a match, there is no skew, otherwise, a skew exists; (4) based on the values of the received data, and TCTL 140, determine if the skew is an early skew or a late skew; and (5) based on the results of (4), correct the skews.

[0035] The above five tasks make up the three major portions of the circuit to de-skew the transmit data, namely the search for the training sequences (tasks 1 and 2), the determination of early or late skews for every bit in the data bus (tasks 3 and 4), and the data path to correct any possible skews.

[0036]FIG. 6 is a block diagram of circuitry 600 according to an exemplary embodiment of the present invention for correcting data skew on a 16 bit data bus such as DataIn[15:0] 604.

[0037] Among other components, circuitry 600 comprises a multiplexor 620 and three 16-bit data registers namely a first register 611, a second register 612, and a third register 613. Multiplexor 620 is a 3:1 mux having three inputs and one output. The first input is coupled to an output port DataReg1[15:0] 605 of first register 611. The second input is coupled to an output port DataReg2[15:0] 606 of the second register 612 while the third output is coupled to an output port DataReg3[15:0] 607 of the third register 613. Further, DataReg1[15:0] 605 is connected to the only input of the second register 612 while DataReg1[15:0] 606 is coupled to the input of the third 613.

[0038] A 16 bit data bus DataIn[15:0] 604, is registered three times at DataReg1[15:0] 605, DataReg2[15:0] 606, and DataReg3[15:0] 607. The data from the above three registers go through mux 620 with two selection lines, ahead[15:0] 609 and behind[15:0] 610, and the output of the mux 620 is the de-skewed data DataOut[15:0] 608. For each bit on the data bus, if there is no skew, the data on DataReg2[15:0] is selected. If the bit is ahead by 1 bit, the data on DataReg3[15:0] is selected. If the bit is behind by 1 bit, the data on DataReg1[15:0] is selected. The selection lines, ahead[15:0] 609, and behind[15:0] 610, are determined in the control logic portion of the circuit. One of ordinary skill in the art will realize that circuitry 600 is illustrative and may be replaced by other circuits consistent with the spirit and scope of the present invention.

[0039]FIG. 7 shows a state diagram (machine) 700 for searching the training sequences in accordance with an exemplary embodiment of the present invention.

[0040] State machine 700 initializes in an idle 110 state where there is no training sequence. When the first pattern of the Transmit Control and the Transmit Data {tctl, tdat}=1_(—)0000_(—)1111_(—)1111_(—)1111 is detected (as shown in cycle 2 in FIG. 2), state diagram 700 enters a 1st 8 state 120 where a pattern of eight consecutive patterns of {tctl, tdat}=1_(—)0000_(—)1111_(—)1111_(—)1111 in eight clock cycles are anticipated. If during this period of time, any received pattern is not 1_(—)0000_(—)1111_(—)1111_(—)1111, state machine 700 goes back to idle 110 state. When eight consecutive training sequences are received, there are two possibilities for the next pattern: (1) the 9th pattern is either the training pattern again, or (2) it is not the training pattern any more.

[0041] For the first situation, the state machine goes to a 9th 112 state and for the second situation, state machine 700 goes to an E&L1 116 state. 9th 112 state corresponds to either a no skew situation or one of the situations in FIGS. 2 or 3, where there are either all early skews or all late skews. The E&L1 116 state corresponds to the situation in FIG. 4, where the skews are both early and late.

[0042] From 9th 112 state, if the next pattern is the training pattern again, that means all 10 patterns received are training patterns, and there is no skew detected. Thus the state machine enters the noskew 114 state and from there it goes back to idle 110 state. Another possibility from 9th 112 state is that the 10th pattern is not the training pattern. In this situation, if TCTL 140 is low, the corresponding bit is late by 1 clock cycle, and the state machine goes to late 113 state where it goes back to idle 110 state in the next clock cycle. If TCTL 140 is high, the corresponding bit is early by 1 clock cycle, and the state machine enters an early 115 state from where it goes back to idle 110 state. The situation in FIG. 5, where both early and late skews take place, are covered in E&L1 state 116 and E&L2 state 117. The state machine goes back to idle 110 state from E&L2 117 state.

[0043]FIG. 8 is a block diagram of a control circuitry 800 for the selection lines of multiplexor 620 of FIG. 6.

[0044] Although not shown, control circuitry 800 comprises logic circuitry implemented by known logic techniques based on desired inputs and outputs of the present invention. In FIG. 8, control circuitry 800 receives three inputs namely de-skewFSM[2:0] 802, TCTL 140 and dataReg1[i] 806 where (i=0, 1, . . . , 15). The outputs of control circuitry 800 are selection lines, ahead[i] 808 and behind[i] 810, where ahead[i] corresponds to 609 and behind[i] is 610 in FIG. 6.

[0045] Referring to FIG. 7, the logic for control circuitry 800 is obtained using state machine 700. The values of ahead[i] and behind[i] can be changed only when de-skew FSM[2:0] 802 is in one of the following states: noskew 114 state, late 113 state, early 115 state, E&L1 state 116 state or E&L2 state 117.

[0046] The combination of the circuitry 600, state machine 700 and circuitry 800 of FIGS. 6, 7, and 8 respectively make up the de-skew circuit. As evident in FIG. 6, the longest delay in this de-skew data path is from DataIn 604 through the third data register 607 and it takes three clocks for DataIn to get to the third data register. For timing concerns, it is the best to register the output of DataOut, 606. Thus a total of 4 clock cycles delay may occur to the data going through the de-skew logic.

[0047] In this fashion, the present invention provides a circuit and method for de-skewing data in a communication system. While the above is a complete description of exemplary specific embodiments of the invention, additional embodiments are also possible. For example, the above discussion can easily be extended to a skew worse than +/−1 bit time.

[0048] For the case of a maximum skew of +/−2 bit time, the data path portion of the de-skew circuitry 900 is shown. In FIG. 9, five levels, instead of three levels as in FIG. 6, of registers are needed to store the possible early or late data. A generic circuit for correcting bit arrival time is shown in FIG. 10. Depending on the maximum skew time, N levels are employed for correcting the skew where N is the levels of registers. As shown, the number of ahead selection lines is (N−1)/2 while the number for the behind selection lines is also (N−1)/2. Modifications for the corresponding state machine and selection lines logic can easily be obtained by one of ordinary skill in the art. It should be observed that while the description of the present invention has been with regard to sending a training sequence in the transmit direction, the training sequence can be sent in the receive direction as well. Furthermore, methods and circuitry presented herein are not limited to a specific SONET system, and may be applied to other types of data communication networks using varying interface standards.

[0049] Therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims along with their full scope of equivalents. 

What is claimed is:
 1. A method of de-skewing data in a data communication system having a first chip for communicating a plurality of data-bits to a second chip through a data-bus, the method comprising: forwarding a sequence of training bits from the first chip to the second chip; receiving the sequence of training bits at the second chip; comparing the sequence of training bits received to the sequence forwarded in order to determine if one training bit has a data skew; if the training bit is not skewed, selecting a first input (the no-skew input) for receiving the plurality of data-bits; if the training bit is skewed, determining whether there is a late skew or an early skew; if a late skew exists, correcting the late skew by selecting a second input (the late skew input) for receiving the plurality of data-bits, wherein the data-bits at the second input are at least one clock cycle earlier than the data-bits for the first input; and if there is an early skew, correcting the early skew by selecting a third input (the early skew input) for receiving the plurality of data-bits such that the data-bits at the third input are at least one clock cycle later than the data-bits at the first input.
 2. The method of claim 1 wherein the communication system is a synchronous optical network (SONET).
 3. The method of claim 1 wherein the first chip is a system chip for performing protocol conversion and the second chip is a framer for framing and de-framing Internet protocol packets.
 4. The method of claim 1 further comprising searching data on the data-bus in order to detect the training sequence.
 5. The method of claim 1 wherein the data-bits at the second input are at least one clock cycle later than data-bits on the data-bus.
 6. The method of claim 1 wherein the data-bus is a 16 bit data-bus.
 7. A method for de-skewing data in a communication system having a system chip for transmitting a plurality of data-bits via a data-bus to a framer chip, the method comprising: receiving a sequence of training bits at the framer; determining whether a data skew exists by comparing the sequence of training bits received to a known sequence of training bits; and selecting any one of three inputs to receive the plurality of data-bits, wherein a first input is selected if there is no data skew, a second input is selected if there is a late skew, or a third input is selected if an early skew occurs.
 8. The method of claim 7 wherein the data-bits at the second input are at least one clock cycle earlier than the data-bits for the first input.
 9. The method of claim 7 wherein the data-bits at the third input are at least one clock cycle later than the data-bits at the first input.
 10. The method of claim 7 wherein the data-bits at the second input are at least one clock cycle later than data-bits on the data-bus.
 11. The method of claim 7 wherein the data skew has a maximum skew of +/−1 clock cycle.
 12. A circuitry for de-skewing bit arrival times on a data-bus, the circuitry comprising: multiplexing logic circuitry having a single data output port, a data select port, and first, second and third data input ports; a first register, having a data input port for coupling to the data-bus and a data output port for coupling to the first data input port of the multiplexing logic circuitry; a second register having a data input port for coupling to the data output port of the first register, and having a data output port for coupling to the second data input port of the multiplexing logic circuitry; and a third register having a data input port for coupling to the data output port of the second register, and a data output port for coupling to the third data input port of the multiplexing logic circuitry, the multiplexing logic circuitry receiving first, second and third data input signals from the data output ports of the first, second and third registers, respectively, and selectively forwarding any one of the first, second and third data input signals to its single data output port.
 13. The circuitry of claim 12 wherein the data select port comprises first and second select lines, and wherein the circuitry further comprises control logic circuitry having first and second data output ports coupled to the first and second data select lines respectively of the multiplexing logic circuitry such that the control logic circuitry selects the first data input signal if there is a late skew, or selects the second data input signal if there is no data skew, or selects the third data input signal if an early skew occurs.
 14. A multiplexor logic circuitry for de-skewing data on a data-bus, the multiplexor comprising: memory; and logic circuitry, for receiving a first data input signal from a first register, and for receiving a second data input signal from a second register, and for receiving a third data input signal from a third register, said multiplexor selecting the first data input signal if there is a late skew at the data-bus, or selecting the second data input signal if there is no data skew, or selecting the third data input signal if an early skew occurs.
 15. The circuitry of claim 14 further comprising a first register having a data input port coupled to the data-bus and having a data output port for providing the first data signal; a second register having a data input port coupled to the data output port of the first register, and having a data output port for providing the second data signal; and a third register having a data input port coupled to the data output port of the second register and having a data output port for providing the third data signal.
 16. The circuitry of claim 15 further comprising a fourth register having a data input port communicably coupled to the data output port of the third register, and having an data output port coupled to a data input port of a fifth register.
 17. The method of claim 16 wherein the data on the data-bus skew has a maximum skew of +/−2 clock cycle.
 18. The method of claim 14 wherein the data on the data-bus skew has a maximum skew of +/−1 clock cycle.
 19. The method of claim 14 further comprising searching the data on the data-bus in order to detect the training sequence. 